Are you passionate about creating cutting-edge digital designs and ensuring their flawless functionality? We are seeking a skilled SystemVerilog Verification Engineer to join our dynamic team. In this role, you will leverage your expertise in SystemVerilog, UVM, and Testbench development to drive the verification process and ensure the robustness of our designs.
JOb Location - Santa Clara, CA
Key Responsibilities:
Utilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.
Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.
Conduct full-chip and SoC simulations to validate design functionality and performance.
Demonstrate expertise in subsystem verification, encompassing controllers and PHY components.
Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality.
Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe.
If you're ready to take on exciting challenges in the field of digital design verification and contribute to groundbreaking projects, we encourage you to apply now!