DFT Engineer at ACL Digital in San Jose, California

Job Description:

• 5+ years of experience of working in DFT.
• Understanding basics of DFT structures, MBIST, Boundary Scan Tap Controller
• Hands on experience with industry standard ATPG tools, MBIST, simulation and debugging.
• Hands-on experience with Verilog behavioral RTL and Gate level net list.
• Generating, verifying, and debugging test patterns to test the designs and firmware for new FPGA families.
• Improving, extending, and porting existing manufacturing test designs to all FPGA family members.
• Test specification, plan, and documentation.
• Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN)
• Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route)
• Good programming skill/Firmware development skills with C, C++/assembly will be a big plus.
• Strong analytical and problem-solving skills.