Senior Front-End ASIC Design Engineer at ATR International in San Jose, California

Job Description:

<b>Job Description:</b><br><br> We are seeking a Senior Front-End SoC/ASIC Design Engineer for our SoC business unit <br><br>Responsibilities Include but are not Limited to:<br><br>* Support customer's design through all phases of ASIC execution at Company.<br><br>* Ensure designs meet product Performance-Power-Area-Schedule requirements Tasks may include Architecture / micro-Architecture; Logic Design; RTL integration and coding; Lint/CDC/DFT checks; Synthesis & supporting timing-closure; Contribute to and support Verification; Supporting Firmware and FPGA teams; Silicon bring-up <br><br>* Ensure deadlines for project milestones are met while maintaining quality.<br><br>* Work effectively with internal and external (including customer and vendors) teams (Note: The COmpany has teams located globally).<br><br>* Display a results-focused attitude and accomplish Company/Team-goals.<br><br><b>Requirement:</b><br><br>Required/Desired Qualifications:<br><br>* Bachelor's Degree in EE or similar degree.<br><br>* 5+ years of professional design experience, provided the work experience is solid micro-architecture and front-end design.<br><br>* Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable).<br><br>* Skills Required - Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support.<br><br>* Technical document writing skill<br><br>* Teamwork, dedication, collaborative, strong communications, and interpersonal skills.<br><br>* Ability to meet stringent deadlines and project timelines.<br><br>* Skills Strongly Desired - SoC Architecture experience Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA.<br>#PandoPandoLogic. Keywords: ASIC Design Engineer, Location: San Jose, CA - 95157