This startup in Mountain View, CA is on a mission to become THE computing platform for GenAI. Founded by highly respected engineers that were instrumental in Google's AI capabilities. They are building hardware by combining deep domain experience for large language models, graphics processing units and other machine-learning models, enabling developers and programmers to make artificial intelligence better, faster and cheaper.
They are looking for a LeadSOC Architect to join their team and help develop top-tier silicon for high-performance and sustainable GenAI. In this role, you will be instrumental in delivering high-performing and functionally accurate silicon architecture at the full chip or subsystem level for products involving compute, memory management, high-speed connectivity, and other key technologies.
This is a full-time hybrid role (Tues-Thurs) in the Mountain View, CA office.
Compensation: $300k-$400k base salary + equity + benefits
Job Responsibilities
Create architecture specifications, pseudo code, working code, and other documentation to describe key functions within the system.
Collaborate closely with micro-architects, designers, physical designers, verification engineers, and others throughout chip project phases to ensure that architectural descriptions can be implemented in silicon.
Partner with software and system architects to develop a silicon architecture optimized for software and system-level considerations, using a working-backwards approach.
Conduct performance analysis of the architecture using tools like software models, design simulations, emulation, and prototyping.
Contribute to the development of test plans for pre- and post-silicon verification and validation efforts.
Interact with third-party partners on IP and technology sourcing and integration into products.
Engage with customers to gather feedback on specific features and collaborate on defining product aspects.
Job Requirements
Demonstrated ability to produce architecture specifications, pseudo code, working code, and related collateral for key functionalities within silicon systems.
Experience collaborating closely with micro-architects, designers, physical designers, verification engineers, and other stakeholders to ensure feasibility of implementing architectural designs in silicon.
Proven track record in working with software and system architects to develop silicon architectures that align effectively with software and system-level requirements, utilizing a backward-compatible approach.
Proficiency in conducting performance analysis of architectures using tools such as software models, design simulations, emulation, and prototyping.
Strong capability to contribute to the development of comprehensive test plans for both pre- and post-silicon verification and validation efforts.
Experience interacting with third-party partners to integrate IP and technologies into product lines.
Ability to engage with customers to gather feedback on specific features and collaborate on defining product specifications.
All candidates must be authorized to work in the United States and work from their offices in Mountain View Tuesdays-Thursdays.