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Boeing Research & Technology is currently seeking a Digital Integrated Circuit Physical Design Engineer (Associate, Mid-Level or Senior) with experience developing complex, high-performance ASICs, FPGAs, and SoCs (e.g. custom multicore processors, digital signal processors) for military/aerospace or other safety-critical systems. This position will be located in Huntington Beach, California.
We are Boeing Research & Technology (BR&T): Boeing's global research and development team creating and implementing innovative technologies that make the impossible possible and enabling the future of aerospace. We are engineers and technicians, skilled scientists and bold innovators; Join us and put your passion, determination, and skill to work building the future! #TheFutureIsBuiltHere #ChangeTheWorld
Within BR&T, Boeing's Solid State Electronics Development organization (SSED) performs microelectronics technology development and design for aerospace systems. We develop digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic systems. These systems are used on Boeing airborne, terrestrial, and satellite platforms. Designs are implemented with state of the art semiconductor process technologies including CMOS, GaAs, GaN, and SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test) in house. SSED has numerous microelectronics projects, funded both by internal Boeing customers and external Government Science and Technology (S&T) customers. SSED's large staff of microelectronics engineers conduct research and designs microelectronics hardware in support of these projects.
Position Responsibilities:
Collaborate with the design team to understand the specifications and requirements of the IC design project.
Perform physical design tasks including floor planning, power planning, placement, clock tree synthesis, routing, and timing closure.
Utilize Cadence or Synopsys EDA tools to implement and optimize physical design aspects of the IC.
Conduct physical verification tasks such as DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check) to ensure design integrity and manufacturability.
Optimize power, performance, and area (PPA) metrics through various techniques such as clock gating, power gating, and voltage scaling.
Analyze and resolve timing-related issues, including setup and hold violations, and perform static timing analysis (STA) to achieve timing closure.
Stay updated with the latest advancements in physical design methodologies, tools, and technologies, and propose innovative solutions to enhance design efficiency.
Document design methodologies, guidelines, and best practices to ensure knowledge sharing within the team.
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed location options.
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret clearance Post-Start is required.
Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science
1+ years of experience in the design/development of integrated circuits
3+ years of related work experience or an equivalent combination of education and experience
5+ years of related work experience or an equivalent combination of education and experience
Solid understanding of digital IC design concepts, physical design methodologies, and EDA tools such as Cadence or Synopsys.
Proficiency in scripting languages such as Tcl, Perl, or Python for automation and design flow enhancement.
Experience with industry-standard physical design tools, including floor planning, placement, routing, and timing closure.
Familiarity with physical verification tools such as Calibre or IC Validator for DRC, LVS, and ERC checks.
Strong analytical and problem-solving skills to identify and resolve design-related issues.
Excellent communication and teamwork skills to collaborate effectively with cross-functional teams.
Knowledge of low-power design techniques and methodologies is a plus.
Experience with advanced process nodes (e.g., 7nm, 5nm, or below) is desirable.
Experience developing digital or analog/mixed-signal ICs for extreme environment applications (e.g. radiation-hardened, extreme low/high temperatures, ultra-long lifetime)
Active security clearance
Typical Education/Experience:
Associate
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 2 or more years' related work experience or an equivalent combination of technical education and experience (e.g. Master). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Mid-Level
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Senior
Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 9 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD+4 years' related work experience, Master+7 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Relocation:
This position offers relocation based on candidate eligibility.
Drug Free Workplace:
Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies .
Shift Work Statement:
This position is for 1st shift.
At Boeing, we strive to deliver a Total Rewards package that will attract, engage and retain the top talent. Elements of the Total Rewards package include competitive base pay and variable compensation opportunities.
The Boeing Company also provides eligible employees with an opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work.
The specific programs and options available to any given employee may vary depending on eligibility factors such as geographic location, date of hire, and the applicability of collective bargaining agreements.
Pay is based upon candidate experience and qualifications, as well as market and business considerations.
Summary pay range for Associate Level: $85,850 - $116,150
Summary pay range for Mid-Level: $104,550 - $141,450
Summary pay range for Lead: $126,650 - $171,350
Applications for this position will be accepted until November 25th 2024
Export Control Requirements: U.S. Government Export Control Status: This position must meet export control compliance requirements. To meet export control compliance requirements, a "U.S. Person" as defined by 22 C.F.R. §120.15 is required. "U.S. Person" includes U.S. Citizen, lawful permanent resident, refugee, or asylee.
Export Control Details: US based job, US Person required
Equal Opportunity Employer:
Boeing is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, physical or mental disability, genetic factors, military/veteran status or other characteristics protected by law.