Principal Signal and Power Integrity Engineer at Kforce Inc in Chandler, Arizona

Job Description:

RESPONSIBILITIES:

Kforce's client, a growing and established engineering technology company is seeking Senior or Principal Signal and Power Integrity Engineers in Chandler, AZ.

Summary:
We are working directly with the Hiring Manager on this search assignment. We have been working with this client for several years and have made numerous placements. We are seeking someone with a strong experience in signal and power integrity related to semiconductor IC package design or similar. This position is hybrid remote (3 days in office and 2 days from home).

Responsibilities:

• As a Senior and Principal Signal and Power Integrity Engineer (SI/PI), you will work with IC package design engineers to provide design solutions for high-speed and low speed signals, clocks, power delivery signals, and power and ground planes


• Provide routing guidelines for high-speed, low-speed, power signals, power, and ground planes from bumps to balls


• Work directly with our customers, package design engineers, simulation engineers, business units, R&D, and assembly


• Provide package layer counts, stack ups, materials, impedance control, test impedance targets, and optimizing net assignments for signals


• Senior or Principal SI/PI Engineers will perform SIPI simulation/optimization to make sure critical signals meet their required specifications


• Signal integrity analysis of frequency and time domain simulations for high-speed signals and low speed signals following specifications


• Optimize single ended or differential Insertion loss, return loss, X-talk, and power sum X-talk for differential signaling groups and protocols


• IR_DROP simulation for the power rails from bumps to balls


• AC frequency sweep simulation to optimize the high RLC traces to the lower by achieving low resistance and inductance traces


• Power plane resonance to measure the resonances of the package plans


• PDN frequency domain and transient time domain analyses

REQUIREMENTS:

• Bachelor's or Master's degree in Electrical Engineering, Physics, Computer Engineering or similar field


• At least 6 to 10+ years of Signal and Power Integrity (SI/PI) Engineering experience preferably at the IC level but will consider at the board level


• Experience with package layout tools such as Cadence APD, SiP, or similar tools is a plus or similar tools


• Experience with high-speed bus design compliance such as DDR5, PCIe5, 56 GBPS and 112 GBPS PAM4 would be ideal


• Strong background in the application of Electromagnetics and High-Speed Transmission Line principles related to signal and power integrity


• Proficiency in time and frequency domain modeling and use of 2D and 3D simulation tools such as Ansys HFSS, SIwave, Cadence/Sigrity, ADS


• Demonstrated and effective verbal/written communication skills


• Excellent analytical and problem-solving skills


• Ability to perform as an individual contributor and team player


• Experience working with customers, global design and simulation teams and/or EDA tool vendors is a plus but not required


• Experience/knowledge of next generation advanced high speed package design/simulation to meet electrical performance or similar is a plus but not required


• Understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signal/ground placement to improve the performance is a plus but not required

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless
and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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