Overview: candidate has to have experience in RF Design Verification.
We are seeking an experienced RTL (Register Transfer Level) Development Engineer with expertise in FPGA design and extensive knowledge of Xilinx/AMD tools, including Vivado. The successful candidate will play a critical role in the design, development, verification, and implementation of FPGA-based solutions for complex systems. This role requires a deep understanding of FPGA architecture, RTL design, simulation, and synthesis, as well as proficiency in Vivado for hardware design, debugging, and verification.
Key Responsibilities:
Required Qualifications:
Education: Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
Experience:
10+ years of hands-on experience in RTL design for FPGAs, including Xilinx/AMD devices.
Extensive experience with Xilinx Vivado Design Suite, including synthesis, simulation, and debugging.
Solid understanding of FPGA architecture, timing analysis, and clock domain crossing (CDC) techniques.
Expertise in VHDL/Verilog/SystemVerilog coding for RTL design.
Experience with FPGA verification methodologies (simulation, constrained random testing, etc.)
Preferred ?ualifications:
Experience with Xilinx Zynq SoC (including Zynq Ultra Scale+) for hardware-software integration.
Proficiency in Vivado HLS (High-Level Synthesis) and familiarity with C/C++algorithm conversion into hardware.
Familiarity with industry standards such as AXI, PCIe, Ethernet, or other high-speed interfaces.
Knowledge of FPGA design for signal processing, communication systems, or AI/ML accelerators.
Familiarity with TCL scripting and automation in Viv ado.
Experience with embedded system design and development