Requirement: Verification JD: • Expert on the System Verilog and Advanced knowledge of HVL methodology (UVM) • Must setup up the verification environment, Test bench development, test plan and coding from scratch. • Experience on any of the below protocols is added advantage:
o DDR/LPDDR
o PCIE • Define ASIC/SoC verification strategy • Full chip TB Architecture definition • UVM based test bench development • SV functional coverage, Assertions coding • Test case development, coding, execution, bug analysis and end to end ownership. • Experience in Perl/Shell scripting • Should Co-ordinate with design team counterparts in RTL design.