RTL Design Verification Engineer at Net2Source Inc. in Bellevue, Washington

Job Description:

• Plan develop and implement comprehensive test benches in System Verilog to validate RTL module functionality across various scenarios
• Execute test benches consistently identifying and documenting potential issues and bugs discovered during simulation
• Perform RTL simulations using tools like ModelSim or QuestaSim to verify design accuracy and troubleshoot errors
• Interpret and analyze state machine and module implementations from RTL code to identify various scenarios for targeted testing
• Utilize shell bash scripting to streamline and automate the test execution process enhancing workflow efficiency
• Conduct detailed RTL code reviews in alignment with model diagrams offering constructive feedback to improve design fidelity
• Actively participate in design review meetings contributing insights and recommendations to ensure robust design architecture