Responsibilities: • Execute electrical, functional, & system tests of DDR5 and LPDDR5x memory sub-system test plans as part of a lab based post silicon platform engineering team • Analyze & debug electrical and functional test data to drive into production SOC and system solution decisions. • Develop DDR5 and LPDDR5x technical test plans and tools to support platform level silicon bring-up and the validation execution. • Supports lab functions including rework, inventory, & system test of platforms
Skills required: • BS-EE / BS-CE / Masters plus at least 1 years directly related experience. An advanced degree will be considered a plus. • Demonstrated technical expertise in the development and execution of platform level memory interface electrical and functional test plans • Knowledge of PC architectures and system technologies. • Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout design files • Good written and oral communication skills, with the ability to communicate with a variety of engineering disciplines and management.