As a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.
You will work with 3rd party IP vendors to integrate Memory BIST, scan, PHY I/O BIST, and other DFT logic into a streaming scan fabric with a sequential scan compressor/decompressor
You will work with DFT Solutions Vendors to port those patterns at the top-level, to implement Memory BIST interface in high performance processor IP, and to implement high-speed I/O for the logic scan test.
You will work with Physical Designers to validate the DFT timing constraints, RTL Designers to verify test design rules, Test Engineers to bring up the patterns on the ATE Automated Test Equipment
You will help develop and deploy DFT methodologies for our next generation products.
Experience in Scan and iJTAG
Key Qualifications
MSEE or equivalent experience
7+ years of experience in DFT or related domains
You will have a solid knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG and fault simulation
Possess excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Have good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired