STA Engineer at ACL Digital in Longmont, Colorado

Job Description:

1. Develop and manage block and SoC timing constraints, ensuring robust STA setup and signoff for multi-corner, multi-voltage designs.
2. Own timing flow and execution, including timing budgeting, repeater planning, constraints generation, and exception handling.
3. Perform full-chip Static Timing Analysis (STA) and drive convergence at block and SoC levels.
4. Collaborate with design teams to understand STA constraints, timing closure challenges, and ensure smooth execution.
5. Work closely with physical implementation teams to debug timing failures and improve Quality of Results (QoR).
6. Expertise in USA-based ASIC methodologies, CAD tools, and industry-standard EDA tools such as Synopsys Design Compiler (DC) and PrimeTime for STA.
7. Strong understanding of multi-voltage design and experience in low-power and multi-power mode STA closure.
8. Proficiency in scripting languages such as TCL, Perl, or Python to automate design flow and analysis.
9. Hands-on experience in Physical Design implementation is a plus.
10. Strong analytical and problem-solving skills, with the ability to handle multiple projects and collaborate with geographically distributed teams