Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs.
Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
Engaging closely with block and SoC design teams to understand the design requirements, STA constraints, and convergence challenges.
Engaging closely with physical implementation teams to ensure designs meet QoR and debug timing failures
PREFERRED EXPERIENCE:
10+ years of professional experience in ASIC implementation and CAD methodology, preferably experience closing timing of high performance designs.
Demonstrated ability in areas of ASIC STA constraints generation, timing analysis, timing convergence, and ECOs, at both block and full chip level, is a must
Implementation experience and knowledge handling multi-voltage design is expected. STA closure of low power and multi-power mode designs is an added advantage.
Expertise in industry standard ASIC EDA tools, including Synopsys DC and Primetime is required.
Proficiency in scripting language, such as, TCL, Perl and/or Python
Experience developing scripts to automate design flow, analysis
Hands-on experience with Physical Design implementation is a plus
Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
Strong analytical/problem solving skills and pronounced attention to details.