Design Verification Engineer- San Francisco Bay Area, CA
Data Centers, Memory Chips, AI
Role Brief:
My client is looking for a Principal Design Verification Engineer to lead full chip/block level verification.
Responsibilities:
Own verification plan for a wide range of data center products
Define and implement verification infrastructure
Implement testbenches & monitors using UVM
Collaborate with world-class hardware/software architects to transform product vision
Skillset:
7+ years' verification experience
Successful track record in verifying chips & designs
Strong knowledge of UVM methodology
Experience in DDR/memory verification highly desirable
Deep experience with full chip verification and infrastructure development
This is an exciting opportunity to join an industry leading semiconductor company who have some of the most exciting chip/silicon IP products on the market. If you are looking for a company that will provide you with career progression and offer an excellent compensation package, then this is the job for you.
Location:
San Francisco Bay area, CA
For immediate consideration please send your resume to tom.ridd@lumicity.io