SBT is the exclusive executive recruiting firm for this confidential position.
This confidential company is strategically bringing on a hands-on technical STA lead. In this role, the timing design expert will be collaborating cross-functionally with a talented team of systems HW engineers and SW architects to develop cutting-edge computing systems. This individual will have first-hand involvement in the full lifecycle of complex chip development, solving complex challenges directly affecting tier-one customers.
Technical Responsibilities:
Perform static timing analysis (STA) on digital circuits to ensure timing closure and identify timing-related issues
Develop and maintain STA scripts and tools to automate timing analysis and reporting
Collaborate with design teams to identify and resolve timing-related issues, including clock domain crossing, metastability, and setup/hold violations
Develop and maintain timing models and constraints for complex digital circuits
Optimize timing performance by analyzing and optimizing clock tree, flip-flop placement, and routing
Work closely with physical design engineers to ensure timing constraints are met during the physical design phase
Qualifications
Technical degree in a related engineering field (BS, MS, PhD)
5-10+ years of relevant industry experience
Proficiency in verification languages and methodologies, such as SystemVerilog, UVM
Relevant company backgrounds include: AMD, Meta, Marvell, Cisco, Broadcom, Intel, Qualcomm, and other networking-related companies