Job Description:
Job Opening for Design Automation Engineer in the Bay Area!
Responsibilities:
- Design automation flow support and development
- LEF/DEF generation
- LVS/ERC checks
- Physical verification support and development
- Supporting issues from LVS, ERC, and LPE errors
Requirements:
- BS, MS, or PhD in Electrical Engineering with at least 6+ years of experience with design automation
- Extensive experince with ASIC IP is a must
- Experience developing PDK
- Knowledge of design automation for analog and mixed-signal IP using Cadence Virtuoso
- Experience with process nodes below 7nm
- Use of multiple languages: Shell Scripting, Linux development environment, PERL, RUBY, Tcl, SKILL/SKILL++, C, C++
- Experience with Calibre TVF and SVRF is a must
- Knowledge of EDA formats like LEF/DEF, OASIS, openAccess, and SPICE/SPECTRE
Note:- Extensive design automation experience with Virtuoso and Calibre is a must for this position