Design Verification Engineer at LanceSoft Inc in San Jose, California

Job Description:

Pay Rate: 85/hr to 95/hr on W2

Remote
• Ideally Masters + 5 years or Bachelors + 8 years is preferred
• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++
• Developing UVM based verification frameworks and testbenches, processes and flows
• Automating workflows in a distributed compute environment.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
• Scripting language experience: Perl, Ruby, Makefile, shell preferred. Apply Now