About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions
Responsibilities?:
Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
Collaborate with software teams to define and implement configurable testbenches
Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.
Qualifications:
BS/MS in Electrical Engineering, Computer Engineering or Computer Science
8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
Proficiency in Verilog, SystemVerilog
Familiarity with industry-standard EDA tools for simulation and debug
Deep experience with UVM-based testbenches
Experience with modern programming languages like Python
Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
Understanding of ARM CHI protocol is a plus
Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
Experience with formal verification techniques, emulation platforms is a plus
Excellent problem-solving skills and attention to detail