Our Client is one of the world's largest global Top-tier Semiconductor Company. Their chips are used by some of the biggest names in the tech industry, and they are helping to shape the future of technology - thus, making them a major force in the semiconductor industry.
The ideal candidate will join the NoC Interconnect design team, collaborating with architecture, modeling, silicon, software, and other design teams to create a competitive design. We are looking for hands-on individuals who are dedicated to system performance improvement.
Location: San Diego, California
Job Description:
Drive NoC Interconnect and Memory System architecture and designs to optimize power, performance, and implementation
Shows system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.)
Develop and implement NoC Interconnect. Validate functionality, improve design revisions, and meet performance targets as well as system requirements.
Experience in computer architecture, microarchitecture, and performance
Design experience and knowledge in architecture, RTL design, performance analysis, and power optimization.
Experience in designing the interconnect fail-operational architecture for function safety
Familiarity with the architecture and the micro-architectures of recent ARM processor is a plus
Familiarity with AMBA AXI, CHI, and LPDDR4/5 interfaces/protocols is a plus
INTERESTED?
We are committed to submitting suitable candidates for this vacancy to our client ASAP, for more information contact Renz Moreno at PER Recruitment or send your CV to renz@per-international.com