Responsible for Design Verification of Performance IP technology that dynamically manages frequency and voltage to achieve maximum sustained performance within a given thermal/power envelope for Flagship Smartphone/Compute SOCs
Develop DV test plan based on the specification, come up with an appropriate DV strategy, build scalable test benches/infrastructure, develop test cases to verify the design according to spec
Develop system-level stimulus and checks to verify the system architecture requirements.
Responsible to debug any RTL/GLS/Silicon failures and work with the RTL engineer. Achieve 100% functional coverage
Develop new DV methodologies. Define and execute Formal verification plan to stress the design. Develop driver api in C for use in the CPU subsystem.
Job Requirement
7 + Years of hands-on experience in Design Verification (DV) on Complex IP used in subsystems
Experienced in all the latest DV methodologies: Formal Verification, System Verilog/UVM, Power Aware verification using UPF
Experienced in developing a DV plan based on Functional Specification, building the necessary test bench/infrastructure, developing tests, and verifying design
Strong debugging skills and expert knowledge of industry standard simulation (e.g.: VCS) and debug tools
Hands-on experience with developing formal verification property checks